The present invention relates to testing systems, including testing of VLSI circuits. Specifically, the present invention relates to testing high-speed systems (including testing of high-speed VLSI circuit) using testers that are slower than the high-speed systems (VLSI circuits) that are tested. The present invention is embodied in a method for generating vectors to be used in a slow tester; in a method for testing VLSI devices using a slow tester; and a system for testing VLSI circuits comprising a slow tester.
It should be noted that the background description and the preferred embodiments are described with reference to VLSI circuits. However, it should be clear to a skilled artisan that the system and methods of the present invention can be used for testing in a system using a tester that operates at a speed no more than the speed of the system.
The operating speed of VLSI circuits is continuously increasing. Even small delay faults can cause VLSI circuits to malfunction. The temporal correctness of a circuit design can be ensured by subjecting the circuit to delay testing. To detect timing defects and test the performance of the circuit, pre-generated test vectors are applied to the circuit. These delay-testing vectors need to be applied to the circuit during a test at the circuit""s intended operating speed. However, testers that are currently used in testing VLSI circuits are usually several times slower than the speed of the new VLSI designs.
As can be readily seen, a gap exists between the speed of the VLSI circuit to be tested and the speed of the tester used test the VLSI circuit. However, purchasing high-speed testers that operate at the speed of the new VLSI designs is expensive. The above-mentioned gap between the speed of the testers and high performance designs is unlikely to disappear in the foreseeable future. Therefore, it is important to find ways to test fast VLSI designs on slower testers.
The problem of testing high-speed circuits without high-speed testers has been discussed in conventional literature. See K. D. Wagner and E. J. McCluskey. Effect of Supply Voltage on Circuit Propagation Delay and Test Application. Proc. of ICCAD, pages 42-44, November 1985; S. Barton. Characterization of High-Speed (Above 500 MHz) Devices using Advanced ATExe2x80x94Technique, Results and Device Problems. Proc. of ITC, pages 860-868, October 1989; L. Ackner and M. R. Barber. Frequency Enhancement of Digital VLSI Test Systems. Proc. of ITC, pages 444-451, October 1990; D. C. Keezer. Multiplexing Test System Channels for Data Rates Above 1 Gb/s. Proc. of ITC, pages 790-797, October 1990; H. Hao and E. J. McCluskey. Very Low Voltage Testing for Weak CMOS Logic ICs. Proc. of ITC, pages 275-284, October 1993, V. D. Agrawal, C.-J. Lin, P. W. Rutkowski, S. Wu, and Y. Zorian. Built-In Self-Test for Digital Integrated Circuits. ATxcx9c3T Technical Journal, 73:30-39, March 1994; J. A. Gasbarro and M. A. Horowitz. Techniques for Characterizing DRAMS with a 500 MHz Interface. Proc. of ITC, pages 516-525, October 1994, V. D. Agrawal and T. J. Chakraborty. High-Performance Circuit Testing with Slow-Speed Testers. Proc. of ITC, pages 302-310, October 1995; and D. Heidel et al. High Speed Serializing/De-Serializing Design-for-Test Method for evaluating a 1 GHz Microprocessor. Proc. of ITC, pages 234-238, October 1998.
Conventional strategies for testing high-speed VLSI circuits include:
tester pin multiplexing. See L. Ackner and M. R. Barber. Frequency Enhancement of Digital VLSI Test Systems. Proc. of ITC, pages 444-451, October 1990;
built-in self-test See V. D. Agrawal, C.-J. Lin, P. W. Rutkowski, S. Wu, and Y. Zorian. Built-In Self-Test for Digital Integrated Circuits. ATxcx9c3T Technical Journal, 73:30-39, March 1994;
use of a high-speed clock and shift registers. See D. C. Keezer. Multiplexing Test System Channels for Data Rates Above 1 Gb/s. Proc. of ITC, pages 790-797, October 1990;
use of special test fixtures. See S. Barton. Characterization of High-Speed (Above 500 MHz) Devices using Advanced ATExe2x80x94Technique, Results and Device Problems. Proc. of ITC, pages 860-868, October 1989;
reducing the supply voltage. See K. D. Wagner and E. J. McCluskey. Effect of Supply Voltage on Circuit Propagation Delay and Test Application. Proc. of ICCAD, pages 42-44, November 1985 and See H. Hao and E. J. McCluskey. Very Low Voltage Testing for Weak CMOS Logic ICs. Proc. of ITC, pages 275-284, October 1993;
use of on-chip test circuitry for testing high bandwidth memories. See J. A. Gasbarro and M. A. Horowitz. Techniques for Characterizing DRAMS with a 500 MHz Interface. Proc. of ITC, pages 516-525, October 1994;
adding extra logic;. See V. D. Agrawal and T. J. Chakraborty. High-Performance Circuit Testing with Slow-Speed Testers. Proc. of ITC, pages 302-310, October 1995; and
serializing parallel circuit inputs and de-serializing circuit outputs. See D. Heidel et al. High Speed Serializing/De-Serializing Design-for-Test Method for evaluating a 1 GHz Microprocessor. Proc. of ITC, pages 234-238, October 1998.
Faults that result in a circuit not producing the correct functional results are called stuck-at faults. Faults that lead to increased delay in generating results are called delay faults. A series of vectors are applied in one or more clock cycles to get a circuit to a stage where it may generate a specific fault. A vector set is applied at one clock cycle after the initialization stage in an activation stage to actually generate the fault. The fault that may show up at a flip-flop or at one of the primary outputs is then transmitted out to be observed during a fault propagation stage, which may require one or more clock cycles and vectors.
Unlike conventional stuck-at fault test generation, test generation for delay faults is closely tied to the test application strategy. Therefore, prior to generating test vectors for delay faults, how the test vectors should be applied to the circuit needs to be determined. Two commonly used testing strategies for sequential circuits are slow-fast-slow strategy and at-speed strategy.
Slow-fast-slow testing strategy assumes that the vectors for initialization and propagation of the fault effect are applied at a slow speed. In such slow speeds up the circuit can be considered delay fault-free in these testing stages. See S. Devadas. Delay Test Generation for Synchronous Sequential Circuits. Proc. of ITC, pages 144-152, September 1989; P. Agrawal, V. D. Agrawal, and S. C. Seth. Generating Tests for Delay Faults in Nonscan Circuits. Design and1 Test of Computers, pages 20-28, March 1993; and T. J. Chakraborty, V. D. Agrawal, and M. L. Bushnell. Delay Fault Models and Test Generation of Random Logic Sequential Circuits. Proc. of DAC, pages 453-457, June 1993. Activation of the fault in a slow-fast-slow strategy is performed by applying a fast clock. It should be noted that in the slow-fast-slow strategy, fast simply means that the clock during the activation stage is faster than that in the initialization and propagation stage. Such a fast clock, as discussed in subsequent sections related to at-speed strategies, does not operate at the speed of the circuit that is tested.
At-speed testing strategy assumes that the fault is initialized, activated and propagated under a fast clock. Unlike the fast clock in the slow-fast-slow, at-speed testing strategies have been proposed that assume that the inputs are applied and the outputs are observed at the rated speed of the circuits that are tested. See I. Pomeranz and S. M. Reddy. At-Speed Delay Testing of Synchronous Sequential Circuits. Proc. of DAC, pages 177-181, June 1992, K.-T. Cheng. Transition Fault Testing for Sequential Circuits. Trans. on CAD, 12(12):1971-1983, December 1993; and S. Bose, P. Agrawal, and V. D. Agrawal. A Rated-Clock Test Method for Path Delay Faults. Trans. on VLSI, 6(2):323-331, June 1998. However, the at-speed strategy mention above assumes that a high-speed tester is available. To differentiate between these at-speed testing strategies and the at-speed testing strategies that can be used to test fast designs on slower testers, the former is referred to herein as conventional at-speed testing strategies.
The present invention is specifically related to at-speed testing schemes for slow testers. The speed of the tester is assumed to be k times slower than the speed of the circuits to be tested on it. Herein, k is a positive integer. In such a case, an external or internal fast clock for operating the tested circuit is required. If a fast clock is not available on the tester, an internal fast clock can be generated using the tester""s clock in combination with a phase lock loop or a frequency multiplier. FIG. 1 illustrates the concept of at-speed testing schemes for slower testers. As shown, the at-speed schemes for slow testers belong to two classes:
(1) testing schemes that apply vectors generated under the assumption that a high speed tester is available (i.e., test generation method is independent of the speed of the tester) and
(2) testing schemes that require application of vectors generated for slow speed testers (i.e., constraints are placed on the test generation procedure to accommodate the speed difference between the designs and the tester).
FIG. 2 illustrates the classification of testing strategies. Case k=1 corresponds to a high speed tester while case k greater than 1 corresponds to the case when the tested designs correspond to circuits that are faster than the tester. The doublet waveform method is a type of conventional at-speed testing scheme currently used in practice for testing sequential designs that are up to two times faster than the speed of the tester (i.e., k=2). See R. Huston. Digital Test Engineering: The Practice of Developing Test Programs for Automatic Test and Characterization of Digital Semiconductor Devices. ITC, Tutoral, November 1997. The doublet waveform method can be extended for k greater than 2. However, it requires more complex tester timing resources and results in testers being more expensive.
Presently, limitations in the generation of tester timing prohibit the use of slow-fast-slow schemes for k greater than 2. A key concept behind the slow-fast-slow schemes for k greater than 1 is the application of more than one input vector during one tester cycle. The test sequence is the same as that applied in conventional at-speed schemes. These slow-fast-slow schemes for k greater than 1 require that the test sequence be applied multiple times in one tester cycle; and at each application of the test vector, the responses of only a subset of fault patterns are measured. Compared to the conventional at-speed testing strategies, the slow-fast-slow schemes for k greater than 1 have the same fault coverage but a longer test application time (because the test sequence needs to be applied multiple times).
Test generation for delay faults is closely tied to the test application strategy and to the delay fault model. Several conventional delay fault models have been proposed in the prior art:
transition model; See J. A. Waicukauski, E. Lindbloom, B. Rosen, and V. Iyengar. Transition Fault Simulation. Design and Test of Computers, pages 32-38, April 1987; M. H. Schulz and F. Brglez. Accelerated Transition Fault Simulation. Proc. of DA C, pages 237-243, June 1987; and K.-T. Cheng. Transition Fault Testing for Sequential Circuits. Trans. on CAD, 12(12):1971-1983, December 1993,
gate model; See K. D. Wagner. The Error Latency of Delay Faults in Combinational and Sequential Circuits. Proc. of ITC, pages 334-341, November 1985, and
path delay fault model; See G. L. Smith. Model for Delay Faults Based upon Paths. Proc. of ITC, pages 342-349, November 1985.
In all the above-mentioned conventional delay fault models, the fault has to be propagated to a primary output through some path within the circuit. Paths in a sequential circuit can be divided into two categories:
(1) paths that originate at a primary input (PI) or present state line and end at a primary output (PO), and
(2) paths that originate at a PI or present state line and end at a next state line.
Depending on the kind of path through which a delay fault can be propagated after its activation, delay faults can be divided into two categories:
(1) faults that can be propagated only through paths that end at some primary output (these are called PO-logic faults), and
(2) faults that can be propagated through paths that end at a next state line ( these are called NS-logic faults).
IB.1 Slow-Fast-Slow Testing Scheme
If the slow-fast-slow testing scheme is used on a slow tester, the presence or absence of latches on primary outputs affects the testable set of faults. This is because to observe a fault, after activation, it has to be propagated to some primary output of the circuit. Consider, for example, testing of non-scan designs. The slow-fast-slow methodologies proposed in the prior art can be directly used to test high speed designs on low speed testers if the primary outputs are latched. See S. Devadas. Delay Test Generation for Synchronous Sequential Circuits. Proc. of ITC, pages 144-152, September 1989, P. Agrawal, V. D. Agrawal, and S. C. Seth. Generating Tests for Delay Faults in Nonscan Circuits. Design and1 Test of Computers, pages 20-28, March 1993 and T. J. Chakraborty, V. D. Agrawal, and M. L. Bushnell. Delay Fault Models and Test Generation of Random Logic Sequential Circuits. Proc. of DAC, pages 453-457, June 1993. The test application scheme for non-scan designs with latched PI/PO is shown in FIG. 3(a). The primary inputs can be latched, but it is not essential. The primary inputs are applied and the primary outputs are observed at the tester""s speed. The tester""s clock is also used in the slow stages (fault initialization and fault propagation). The tester""s clock is assumed to be slow enough for the circuit to be fault-free in these stages. Fault activation is performed with a fast clock. Each vector applied to the circuit can be represented as pair V=(Ii, Sj), where Ii denotes the i-th set of primary inputs and Sj, denotes the j-th set of present state values.
Consider the waveform in FIG. 3(b). It illustrates the case when the tester""s dock is two times slower than the operating speed of the circuit under test, i.e., k=2. Also, it is assumed that the test sequence for the target fault consists of two initialization vectors (V1 and V2), one activation vector (V3) and two propagation vectors (V4 and V5). Initialization vectors, V1 and V2 are applied at times T1 and T2 respectively. It should be noted that initialization vector can be applied only at the tester""s slow clock. After the application of the activation vector at time T3, the values of the primary outputs and next states are latched at time T4. Here, it should be noted that the activation vector is applied using the fast clock. Next, the propagation vectors V4 and V5 are applied at times T5 and T6, respectively. Again, the propagation vectors are applied only at the tester""s slow clock. Finally, at time T7, the primary outputs are observed.
Since the primary outputs can be latched at the end of the activation phase, the slow-fast-slow methodology can test both NS-logic and PO-logic faults. When the primary outputs are not latched, PO-logic faults might not be testable on a slow tester using slow-fast-slow testing scheme. Only faults that are larger than a certain size can be tested. For example, PO-logic faults in the circuit in FIG. 3(a) have to be larger than T5xe2x88x92T4 to be testable.
A comparison of classes of path delay faults that can be detected by slow-fast-slow and at-speed testing schemes for the case when a fast tester is available has been discussed in the prior art. See S. Majumder, V. D. Agrawal, and M. L. Bushnell. Path Delay Testing: Variable-Clock Versus RatedClock. Proc. of Int""l Conf. on VLSI Design, pages 470-475, January 1998. The results might not be valid for the case when the tester is slower than the tested designs (k greater than 1).
IB.2 Conventional At-Speed Testing
In any at-speed testing scheme, the fault is assumed to be present in all test stages. Conventional at-speed testing schemes require that the primary inputs are applied and the primary outputs are observed at the circuit""s rated speed. In this section, conventional strategies that allow using test vectors generated under conventional at-speed testing schemes are discussed.
In early testers, the pin electronics that are used to stimulate or observe the response of the tested device had central and shared timing resources. See R. Huston. Digital Test Engineering: The Practice of Developing Test Programs for Automatic Test and Characterization of Digital Semiconductor Devices. ITC, Tutorial, November 1997. As the demands for high tester timing accuracy were increasing, it was becoming clear that tester architectures with central and shared timing resources could not satisfy the edge accuracy requirements. This led to testers with the per-pin architecture. These testers allow for easier test program generation since each tester pin is provided with its own, independent timing resources. However, providing each tester pin with its own timing resources is the main cause of the testers being expensive. It is thus clear that more complex per-pin architectures leads to higher cost testers.
Generating input stimuli and strobing the outputs requires application of timing events or timing markers. The per-pin architecture testers provide separate timing markers for each tester pin. Also, there could be more than one timing marker available during one tester cycle. Testers commonly in use usually have four timing markers per tester cycle. More expensive testers might have five, six or more timing markers per cycle. Timing markers allow application of multiple input patterns in one tester cycle. The doublet waveform method that is currently used in practice is based on applying multiple input patterns in one tester cycle. See R. Huston. Digital Test Engineering: The Practice of Developing Test Programs for Automatic Test and Characterization of Digital Semiconductor Devices. ITC, Tutorial, November 1997. The doublet waveform method allows testing devices at frequencies that are up to two times higher than the maximum frequency of the tester. In such cases, it is assumed that a free running clock with frequency matching the design frequency of the tested circuit is available.
The doublet waveform method applies two input patterns to the tested circuit during one tester cycle. Generating two patterns per tester cycle requires two timing markers. FIG. 4 illustrates application of value 0 followed by value 1 during one tester cycle. Timing markers used for generating this input stimuli are denoted as t1 and t2. The outputs are usually observed using window strobing. In window strobing the output pin is monitored during an interval (or window) of time. Observing one output using window strobing requires two timing markers. If the tester has four timing markers available per tester cycle and two timing markers are used for generating the input stimuli in the doublet method, then only one window strobe can be performed in the same tester cycle. This means that the outputs in the doublet waveform method have to be observed in two phases. Therefore, the same set of inputs needs to be applied twice. FIG. 5 illustrates the two-phase output strobing. These phases are denoted as phase A and phase B. After the first application of the doublet pattern, the output is strobed in the interval between t1 and t2 (phase A). After the patterns are applied for the second time, the output is strobed in the interval between t2 and the second t1 (phase B).
The doublet waveform method applies two patterns per tester cycle. However, the test sequence needs to be applied twice. The test time can be significantly shortened if a tester has more than four timing markers. For example, on a tester with six timing markers per tester cycle, the observation of the outputs could be performed with only one application of the input pairs since the observation of outputs could be done in one phase. The doublet waveform method can also be generalized for application of more than two vectors per tester cycle. For example, if the tester has five timing markers per cycle, it is possible to test devices whose speed is up to three times higher than the speed of the tester. In each tester cycle, three timing markers would be used for input stimuli and the same patterns would be applied three times to observe the outputs in three different phases. However, the cost of the tester is directly proportional to the number of timing markers per tester cycle and the number of markers is also limited by the tester timing marker regeneration time.
In the above methods, the set of detected faults does not depend on the presence or absence of PO latches since the observation of the outputs can be done after each applied pattern, although in different phases.
The at-speed methods for testing circuits with speeds higher than the speed of the tester described in this subsection do not require any special test generation procedures.
It is therefore desirable to have a tester that can test circuits faster than the testers speed, but that does not incur the additional costs that are described above.
It should be noted that detailed descriptions of scan techniques, scanning algorithms and other related issues, which may be required for a general understanding of the subject matter described herein, can be found in co-pending U.S. application Ser. No. 08/994,430, by Chakradhar, et al, titled Peripheral Partitioning and Tree Decomposition for Partial Scan, which is incorporated herein by reference.
It is an object of the present invention to find ways to test fast designs on slower testers without all the above-mentioned problems that are seen in conventional testers.
It is a specific object of the present invention to provide a class of at-speed testing strategies to reduce the test application time for a slow tester testing a high speed circuit. It is another object of the present invention to provide a tester slower than the speed of the circuit which is tested that uses test vectors that integrates the speed limitations of the tester.
The present invention integrates the tester""s speed limitation with the test generation procedure. Putting constraints on the set of inputs that can be applied to the circuit under test and how the outputs can be observed helps reduce the test application time. It should be noted that, due to the constraints placed on the test generation procedure, these strategies can result in a lower fault coverage.
To meet the objects of the present invention there is provided a method of generating test vectors for detecting faults in a system, said system operating at a system speed, wherein the system is tested using a tester, said tester operating at a tester speed, said tester speed being no more than the system speed, said method taking into account the tester speed by integrating speed limitations of the tester during a test vector generation process.
Preferably, the tester speed is substantially less than the system speed.
Preferably, the system to be tested is a VLSI circuit and the tester speed is no more than a speed of the VLSI circuit.
Another aspect of the present invention is a method of testing high-speed circuits using a tester, said circuits having a circuit speed, said tester having a tester speed, said tester speed being lower than the circuit speed, said testing being done by applying test vectors to the circuit, said test vectors being generated using a model of the circuit while taking into account the circuit design and the tester speed by integrating the speed limitations of the tester.
Yet another aspect of the present invention is a method of testing high-speed circuits using a tester said circuits having a circuit speed, said tester having a tester speed, said tester speed being lower than the circuit speed, said method comprising: estimating the tester speed; estimating the circuit speed; obtaining a model of a design of the circuit; generating test vectors using the model of the circuit by integrating the tester speed and the model of the circuit; applying test vectors generated in step d at the tester speed; and observing outputs generated by the circuit at the tester speed.
Preferably, between applying input vectors and observing outputs the circuit is allowed to run at the circuit speed.
Still another aspect of the present invention is a tester for testing high-speed circuits, said circuits having a circuit speed, said tester having a tester speed, said tester speed being no more than the circuit speed, said tester applying test vectors to the circuit, said test vectors being generated using a model of the circuit while taking into account the circuit design and the tester speed by integrating the speed limitations of the tester.
Preferably, the tester speed is substantially lower than the circuit speed.